FIP is a processor core intended to be implemented in CPLD, FPGA, ASIC or as a standalone processor.

The mix of architectures (registers and stack) makes the processor architecture very simple to use with high-level compilers such as C/C++ compiler which makes the high level programs codes portables between processors.

The variable architecture is designed to fit FPGA and adapted for computing application. This core is designed to combine simplicity and performance for processors, with low utilisation for resources and logic elements.

Advantages:

• Low utilisation of logic elements and resources

• Reduced instruction set

• Reduced size of compiled code

• Faster performance

• Compatibility with high-level compilers and standard programmer’s model

• Simple implementation in low cost CPLD/FPGA