The FIP Processors

The FIP Processors provide simple architecture (patent pending) designed to combine simplicity and performance, with low utilization for resources and logic elements, to fit small FPGA and CPLD.

The FIP Processors architecture is configurable with different parameters to fit the users requirements for speed and performance. this architecture is a mix between stack and registers architecture. The programmer's model of this architecture is compatible with standard programming model.

The FIP Processors  is designed to connect to any Wishbone  compatible devices thru Wishbone buses.

The FIP Processors  C/C++ Compiler is compatible with ANSI-C

 

 

 

 

 

 

As a summary, the advantages of this architecture are enumerated as follow:

  • Low utilisation of logic elements and resources

  • Reduced instruction set

  • Reduced size of compiled code

  • Faster performance

  • Compatibility with high-level compilers and standard programmer’s model

  • Simple implementation in low cost CPLD/FPGA

  • Wishbone connectivity